1. Field
This invention generally relates to digital signal processing circuits, and more particularly to multirate digital processing circuit architectures.
2. Related Art
Discrete time, or digital, signal processing generally performs discrete time processing on data samples representing time sampled analog signals. The data samples accepted by a discrete time signal processor are sampled with a time period that may not be adapted to the frequency spectral content of the analog signal being represented. Some discrete time signal processing algorithms are able to be more efficiently implemented, e.g., by using less memory to implement fewer delay line stages to perform an equivalent processing function, if the discrete time sampling rate is adjusted to more closely match the spectral components of the data being processed.
Adjustment of a sampling rate of a discrete time signal is performed, for example, in multirate discrete time processing systems. Multirate discrete time processing systems generally include processing for resampling the data stream. Conventional resampling generally operates in one of two methods. A first method upsamples and filters a data stream to a much higher sampling rate and then downsamples the filtered signal at the desired processing sampling rate. Another method implements a resampling filter to accept a discrete time data stream at one sampled rate and produces an output data stream that has the desired, and different, sampling rate.
These conventional systems require two reference clocks to control the digital processing hardware, one reference clock that operates at the incoming data sampling rate and another reference clock that operates at the desired sampling rate at which the discrete signal processing is to be performed. If these two reference clock rates are not related by an integer multiple of one another, generation of these two different reference clock signals requires clock generation hardware, which often operates at a high speed and consumes significant current and are often quite costly, to be mostly replicated for each of these two reference clocks. For example, many such applications require two independent Phase Locked Loops (PLLs), each requiring independent Voltage Controlled Oscillators (VCOs) to generate the two reference clocks.